Apply Now    
Job ID: JR0001180
Job Category: Engineering
Primary Location: Austin, TX US
Other Locations:
Job Type: Experienced Hire

Senior Memory Design Engineer

Job Description
A Senior Memory Design Engineer is responsible for the design and implementation of Small Signal Array (SSA)/RF compiler for a System-on-chip (SOC) family of products. Responsibilities would include: - Automate RF build and verification flow for the memory compiler - Design and characterize sub arrays for robust operation at extreme corners - Provide design solutions for highest memory density and lowest power solutions


Minimum Qualifications-Must have a BS, MS or PhD in Electrical Engineering or Computer Engineering -4 years' experience with industry standard memory compiler development and all relevant views for the SOC memories -2 years' experience with scripting (Perl, tcl etc.) to develop the compiler and support or enhance the tool as required -4 years' experience in convergence tools including: formal equivalence verification, static timing methodology for SRAM, RF, race check validation, noise and RV -6 years' experience with transistor level operation, SRAM/ sense-amplifier design, design challenges under process variations and low power circuit techniquesPreferred qualifications-4 or more patents and/or publications

Inside this Business Group

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
Apply Now    

What would you like to do now?

Connect with Us

Get Job Alerts

Get started
Student Center

Find out more about working at Intel

Learn more
Hiring Process

Hiring Process

Learn more

Grow your network of opportunities