Responsible to validate Intel's new 3DXPoint memory to ensure it meets product specifications and functionality before it is productized into a physical chip. Required to work very closely with the analog/RTL designers and architects to implement the low-level RTL design to ensure overall good functionality of the chip. Develop specific test environment/platform, validation methodology and test plans to validate the device by identifying and exercising boundary conditions and special cases in an effort to "break" the chip to find that last elusive bug. Your responsibilities will include (but not limited to):
- Develop and support the full chip test environment and Unit Level Tests
- Debug RTL simulations
- Involve in RTL logic design (in System Verilog)
- Validating the functionality of new architectural features of next generation designs by developing the validation test plan, test content or test tools.
- Developing automated tools or scripts for the pre-silicon validation environment
- Contribute to the definition of higher level device specifications
Inside this Business Group
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.
The applicant must be pursuing a Master’s Degree in Electrical, Computer Engineering or Computer Science.
3+ years of experience in Digital Logic Design and Pre-Silicon Validation experience.
6+ months of experience with:
System Verilog, OVM, UVM and testbench development.
Software design best practices: Design patterns, Object oriented design experience, data structures and algorithms, IDE (Eclipse, visual studio, or similar), make, version control (git).
Developing testplans, write tests and develop coverage points for validation purpose based on high level Architecture spec.
VLSI or Structural and Physical design flow/methodology.