As a Senior Engineer in the PSWE Group, you will design, implement, and maintain software, IP features, timing and verification methods as related to FPGAs for cutting-edge multi-gigabit Transceivers and Phase locked loops (PLLs). You will be part of a dynamic team that defines and develop new algorithms and enhance the software infrastructure of Altera’s Quartus II CAD system to provide best-in-class usability and efficiency of these blocks. You will also work closely with the IC Design teams to define the features needed in the hardware to support next generation features, verification and protocols in these blocks.
Inside this Business Group
The successful candidate's minimum qualifications will include the following:
• BS in Computer Engineering or equivalent
• Strong background in data-structure and algorithm implementation in C/C++
• Understanding of Hardware design, Timing and Verification concepts, UVM knowledge a plus
• Experience with scripting languages such as Python and Perl
• Technical leader with ability to manage project deliverables
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.