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Job ID: JR0000146
Job Category: Engineering
Primary Location: Hillsboro, OR US
Other Locations: California, Santa Clara;
Job Type: Experienced Hire

Senior Physical Design Engineer

Job Description
Candidate will be working as part of a team supporting RTL synthesis and place & route experiments using external vendor tools to improve Intel's product Power, Performance, and Area, for existing and future technology nodes. The candidate is expected to be working in close collaboration with our partners in the process technology and design teams spanning CPU and Graphics. The candidate will be responsible for driving the four fundamental vectors, design, FIP, TFM, and process optimizations to meet/beat PPA targets


Minimum Qualifications:
Master of Science in Electrical Engineering or related discipline.

At least 8 to 10 years of experience in the Industry with
Minimum 8 years experience with RTL synthesis and
Minimum 8 years experience using Place&Route too
Minimum 8 years experience and expertise in CPU and GFx core hardening.

Should have experience working with a team trying to hit performance, power, and area targets.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth

Other Locations

California, Santa Clara;

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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