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Job ID: JR0001183
Job Category: Engineering Management
Primary Location: Taipei, TPE TW
Other Locations: PRC, Shanghai;
Job Type: Experienced Hire

Intel Custom Foundry Tape-out Execution: Full Chip Integration

Job Description

Job Description: The Foundry Product Tape Out Execution is the primary technical interface between the customer and internal engineering teams, with focus on ensuring high quality Customer Tape-out, which meets/beats industry standard throughput. General Focus Areas in this Role: The position is required to work on customer's site to participate the tapeout related tasks including physical implementation, timing signoff, reliability verification and DRC/LVS verification.

- Lead customer Tape-out Execution for advanced lithography nodes

- Participate in development and update of Tape-out quality Checklists and Paranoia

- Interface with customer lead technical engineer(s) and functional area leaders

- Understand customer's technical requests and needs and translate into an Intel Custom Foundry response

- Identify customer's skill and methodology gaps and provide support to enable them to tape-out on Intel process technology

- Ensure industry standard Tape-out throughput is met, and drive reduction opportunities


Qualifications

General Qualifications
- 10+ years of proven success on ASIC tapeout and management experience
- Ability to support COT/ASIC customers from early design stage through tapeout and provide professional recommendation in design stage
- Work with customer as a team to accomplish the tapeout tasks with hand-on EDA tool skill set
- Ability to work well across Intel Custom Foundry and with customer's engineering team
- Strong brainstorming and problem solving skills
- Good organization skills and ability to develop a plan of action to address technical challenges
- Successful applied experience in the areas listed below in the Specific Focus Areas:
Familiar with ASIC design methodology, including hierarchical design methodology, low power design methodology and IP integration check
Familiar with APR flow including floorplan, I/O assignment, power plan full chip CTS topology and ECO methodology
Familiar with STA timing verification flow, reliability analysis flow such as IR/EM drop analysis.
Familiar with Layout verification rule including DRC/LVS/DFM , ESD/Latch-up rule and tapeout cleanup review
Fluent in Chinese, Japanese or Korean is a plus.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth



Other Locations

PRC, Shanghai;

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