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Job ID: JR0000304
Job Category: Engineering
Primary Location: Hillsboro, OR US
Other Locations: Arizona, Phoenix; California, Santa Clara;
Job Type: Experienced Hire

Foundation IP Applications & Solutions Engineer

Job Description
The Intel Custom Foundry group chartered to serve new products, is looking for qualified candidate with alignment and experience in the required areas described below to join its Foundational IP Applications Engineering team. The key function are Memory IP development engineering that involves diverse aspects of enabling and implementation of advanced memory macros for use in target customer products and standard logic cell customer support, training and enablement. Responsibilities of the FIP ASE includes:
Deliver a highly capable first line support and solutions services to our Foundry customers for all the Memory and Library IP product design enablement capabilities we deliver to them
Develop the Memory and Library IP framework, collateral, and processes for quickly ramping our first time customers and external eco-system partners (i.e. ASIC and IP design service providers) on what it takes to implement high quality and proficient designs on Intel based technology
Work with Foundry sales/marketing and internal development teams to define the Memory and Library IP product design enablement capabilities and solutions roadmap that enables us to deliver the most competitive solutions for our Foundry customers.


Minimum of 7 years of design experience with memory and standard cell circuits, layout, technology development and analog design:

- Demonstrate experience in SRAM circuit design with strong foundation in process/design interactions at circuit and layout levels
- Demonstrate experience with working knowledge of memory IP design tradeoff for area/power/performance
- Circuit design expertise to implement and improve existing circuit designs for SRAM assist, dual supplies, - - DRAM building blocks and Fuse design. Exposure and background in NVM memory and 3D stacking desired.
- Demonstrate experience in circuit simulations for memory and analog designs
- Demonstrate experience in memory IP providers and memory compilers including third part vendors desired
- Demonstrate experience in analytical circuit modeling to predict memory macro area/power/speed for design configurations
- Demonstrate experience in large signal memory designs including dual and multi-ported register files, ROM, and queue structures. Demonstrate IP integration experience, ASIC design knowledge and SoC design knowledge.
- In depth understanding of Library IP development on leading edge Si technologies
- Demonstrate knowledge of industry standard views released in standard cell libraries.
Ability to work effectively with global teams in a variety of geographies
-Technical Leadership demonstrated leading major projects with internal and external customers

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth

Other Locations

Arizona, Phoenix; California, Santa Clara;

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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