Pre-Silicon Validation engineer position in the front end design team. Responsibilities includes - • Accountable for the validation of unit/cluster responsible which includes understanding of the design, owing Testplan and validation environments to ensure correctness of design. Also responsible for regression and debug co-ordination • Be able to prioritize, manage risks, evaluate trade-offs and then makes decisions to move forward
Inside this Business Group
You should possess a Bachelor or a Master of Engineering degree with min 1-2 years or more of relevant industry experience. Additional qualifications include: • Should have RTL and/or logic design skills • Familiarity with Verilog/SystemVerilog • Good written and verbal communication skills Desirable qualifications: Knowledge of Processor and/or Graphics designs
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.