The Hard IP group helps Intel's next generation processors bethe smartest in the world and we are looking for a talented engineer to joinour Phy Logic team.In thePhy Logic team, the candidate will be responsible of writing logic block,running pre silicon validation and other quality flow in the block. On thisposition the candidate will have to deliver some IP to SOC using the IRR Intelmethods.Also thecandidate will Learn the PHY core feature and is expected to participate to allthe phases of the next product development from UArch/logic design to LAB EV/SVdebug and production support.
Inside this Business Group
3+ years on Logic design related experience:- SOCintegration flow-Hardware Logic knowledge- Verilog/ VCS / NCSIM / CDC/ Scan- Perl /Unix- LAB equipment/ Logic analyzer
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.