Inside this Business Group
Minimum Qualifications: - BSEE/MSEE and at least 10+ years' experience with the following: - RTL Logic Design experience of Multi-Million Gate ASICs. - Experience with High speed and Low Power Designs. - Experience having power management architecture and power modeling Preferred Qualifications: - Proficiency in Front End Tools and Methodologies. - Experience in VCS-NLP and UPF2.0 - Experience in low power verification and power intent verification - Experience in power modeling and analysis with cellular modem and advanced technology nodes - Experience with Multiple Clock Domains and Asynchronous Interfaces. - Experienced in Synthesis Flows with Standard Libraries and different Process Nodes (e.g., 28nm, 22nm, 16nm/14nm, ...) - Familiarity with Scripting Languages like Gmake/Perl/Tcl/Python. - Experience with Bring Up and Lab Debug of Silicon.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.