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Detailed Position Summary:-Deliver test solutions and module to the manufacturing test program to:-Screen PLL related defects-Tune the PLL to its optimized performance and stability-Enable data collection critical to PLL characterization that is needed for debug, performance monitoring, and learning for future product/processHVM day-to-day:Pre-Silicon:- Definition of how-to-test a certain PLL parameterMay involved meeting with design or test engineers from other products/sites- Writing and launching test in RTL ,system Verilog or Intel-based test writing language-Test results verification and debugMay involve review with peers and design-Conversion of test to test pattern -Development of test program module flowNeeds tester knowledge and scripting (Python, xml)Scripting skills need file parsing, string manipulation, search algorithms and calculation-Integration, validation and release of test module and patterns into test programWill require coordination with test program teamNeed to attend regular meetings for test program team pass down and schedule-Post-Silicon:-Pre-Silicon activities will usually overlap with post-Si work-Characterization or DV of PLL on Silicon in the context of high volume-Perform statistical analysis and conclusions regarding PLL health and performance based on high volumeRequires skills in data mining, data manipulation, and use of statistical tools:SQL, Proficiency in scripting and Unix (Perl/Python), Medium to advance level Excel, JMP-Unit level debug on anomalous or outlier unitsRequires debug skills May require coordination with design and bench DV teamWill require enough knowledge of PLL architecture and operation to be able to design experimentsDOE-Optimization of test module performanceMay require creative solutions to achieve cost-saving and high quality solutions on test implementations-Desired candidates:-Self-driven and strong team player-Makes initiative in working with or helping peers-Strong background on analog circuits (LDO, regulators, basic feedback and filter circuits, PLL, A2D, DAC)-Hands-on Verilog experience-Strong scripting background (Python or Perl)-Proficient on Unix and Excel-Basic test method background (e.g., how to test open/short, leakage)-Knowledge of how a ATE (e.g. timing/levels/patterns)-Data mining and manipulation background (SQL)-Understands statistics and how to statistically present high volume dataBench day-to-day :-software development (python)-data analysis (JMP, SQL)-review data with designers, run experiments-debug scripts written by other people (may require reverse engineering or tracking down contacts)-occasional hardware/board debug when something doesn't work (component goes bad, dip switch moved, jumper fell off, etc)-oc
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.