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Job ID: JR0810021
Job Category: Engineering
Primary Location: Folsom, CA US
Other Locations:
Job Type: Experienced Hire

VPG Pre-Si Verification Engineer

Job Description
Develops pre-Silicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing. Candidate should have good problem-solving, communication, and interpersonal skillsSpecific responsibilities/duties (generic will auto fill with job title): Key Responsibilities: • Responsible for verification of design, architecture, golden models and micro-architecture using advanced verification methodologies • Responsible for understanding the design and implementation, defining the verification scope, developing/maintaining the verification infrastructure (Transactors, Testbenches, BFMs, Checkers, Monitors). • Definition and development of testplans, Functional coverage points, Assertions, Random/Directed tests to validate design • Running RTL simulations, developing testcases to execute the feature testplans debugging design/TB issues • Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes • Work with other cross cluster, full chip teams to ensure seamless integration of verification components


Minimum qualifications and experience:Bachelor’s in in EE and/or CS Engineering or related field plus 6 years of relevant experience. A Master’s degree is preferred.Candidate should have 6+ years of experience with the following:• Solid experience with HVL’s like SystemVerilog, or Specman • Familiarity with OOP’s concepts and OVM/UVM methodologies • Hands on experience with coding and developing testbench components like BFM’s, Monitors and Checkers/Scoreboards. • Good understanding of overall Validation flows tools • Familiarity with Functional Coverage, Code Coverage Assertions concepts methodologies • Preferable but not desired, is some familiarity/experience with Formal Property Verification flows/tools • Possesses good problem-solving, communication, and interpersonal skills Preferred Qualifications and experience:• Knowledge Cache based designs Cache Coherency flows is a big plus • Experience with Perl, Shell scripting, Makefiles, TCL a plus

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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