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Job ID: JR0020556
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations: India, Bangalore;
Job Type:

Analog Design Engineer

Job Description

In this role as Analog Design Engineer in Intel's Platform Engineering Group organization, you will be responsible for the below items focusing mainly on the analog, custom and mixed signal aspects of an IP/Subsystem/SoC design & development

  • Define structural/analog design methodologies and develop design flows
  • Implement structural/analog physical designs and integration
  • Verify structural/analog physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power
  • Oversees definition, design, verification, and documentation for an IP/Subsystem/SoC development
  • Determines architecture design, logic design, and system simulation
  • Defines module interfaces/formats for simulation
  • Contributes to the development of multidimensional designs involving the layout of complex integrated circuits
  • Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing



Qualifications

Qualification:

You must possess a Bachelor/Masters/Ph.d degree in electronics/electrical/communication/VLSI/Microelectronics and/or related engineering/technology with experience in the range of 3 to 15 years in analog and mixed signal circuit design with a focus on high-speed serial I/O interfaces, clock generation circuits or voltage regulators and circuit/design quality & reliability. Publications and patents in relevant fields would be an added advantage. Below are some of the specific expectations for this role

- Solid understanding of microelectronic circuit design fundamentals and semiconductor device physics with experience in design of complex circuit IPs/subsystems

- Expertise in transistor-level analog design, block-level integration and architecture tradeoffs

- Expertise in CMOS analog design, layout and be capable of interfacing with other teams

- Ability to clearly express technical concepts in verbal and written form

- Work experience and knowledge of high-speed serial link interfaces (UPI, PCI-E), including transmitter, receiver, Clock, Data Recovery (CDR), Op-amp circuit design, ADC and DAC circuit design

- Innovative thinking, problem solving, good communication skills, self-discipline and results orientation are critical soft-skills needed

- Experience in designing and analyzing Phase-Locked Loop (PLL) loop response for stability and/or performance would be an added advantage

- Good hands-on knowledge on industry standard EDA tools & HDLs

- Good hands-on knowledge of using scripting languages would be an added advantage

- Hands-on experience in converging complex blocks from RTL to GDSII (100K-1 million gates) with embedded black-boxes
- Exposure to handling APR blocks associated with Analog IP’s like DDR and PCIe would be a plus

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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