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Job ID: JR0009713
Job Category: Engineering
Primary Location: Haifa, IL
Other Locations: Israel, Jerusalem;
Job Type: Experienced Hire

Hardware Backend Leader

Job Description

Leading the physical design cycle up to back-end implementation stage.

Responsibilities & Duties
Leading the entire physical implementation activities of a complete design cycle from RTL to tape-out.
Build and leading new SD team under tight schedule and high quality.

Communication with different groups, internal teams, external vendors and worldwide outsourcing team.

Managing the following SD fields:

  • Floor-planning, clock and power distribution , place & route.
  • Power and noise analysis (EM/IR-Drop/Xtalk).
  • Layout verification (DRC/LVS).
  • Timing sign-off (unit-level/top-level , interfaces).
  • Etc..


Qualifications

- +5 VLSI SD management experience
- +10 years’ experience in physical design of large scale designs.
- In-depth understanding of static-timing analysis – advantage .
- An extensive know-how in clock/power distribution and analysis, RC extraction correlation and place & route – advantage.
- Experience with design practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration – advantage.
- Extensive experience with one of the place & route tools available today – advantage.
- Extensive experience with hierarchical design approach, top-down/bottom-up design, timing and physical convergence – advantage.
- Knowledge in Verilog – advantage.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.



Other Locations

Israel, Jerusalem;

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