IP Logic Design Engineer

The central IP team of Intel's Scalable Performance CPU Development Group SDG located at Massachusetts Microprocessor Design Center is looking for an Experienced Logic Design Engineer to contribute in the high speed IO and/or high performance power delivery/Voltage Regulator IP for Intel's client/Server/Chipset SOC designs.

You responsibilities will include but are not limited to:

• Collaborating with cross discipline stake holders in defining micro-architecture, implementing RTL in System Verilog, validating the design, synthesizing the design and closing timing.
• You will also have an opportunity to work on high-level understanding of the architecture and transistor level analog circuit implementation
• You will contribute to specifications at multiple levels, including the HAS and MAS micro-architecture spec.
• You must be able to balance design trade-offs with modularity, scalability, DFX requirements, chassis compliance, power, area, and performance.
• You will provide IP integration support to SOC customers and represent RTL and the IP team.
• You will mentor and train junior engineers in the IP team from different disciplines.

The ideal candidate should exhibit behavioral traits that indicate:

• Excellent written and verbal communication skills are critical on a small, fast-moving team.
• As part of a growing, dynamic new business, the candidate must be successful working with a small team and manage multiple tasks and changing requirements, in an innovative environment.

Qualifications:

The successful candidate will possess a BS, MS, or PhD degree in Electrical Engineering or Computer Engineering with 5 to 10 years of relevant industry experience in digital VLSI design.

Additional qualifications ideally include:

Low power design, understanding analog design concerns and driving to an optimal solution between analog and digital designs, familiarity with pre-silicon and post-silicon validation.

Experience in the following areas/ skills preferred:

Mixed signal design or validation, Logic design using System Verilog Micro-architecture trade-offs and documentation Low-power design using UPF and clock gating Multiple clock domain design IOSF Sideband and Chassis State machine design TAP Controller and DFX Simulation and debug experience using VCS/Verdi Customer support and debug for SOCs Synthesis and speed path debug Perl / C-shell Standard SOC Design tools and methodologies at Intel

Qualifications

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.