As an ASIC Design Manager, you will lead and manage a team of experienced engineers to execute the ASIC IP development from planning to micro-architecture definition, RTL coding & quality control and IP subsystems integration for the next generation ASIC IP development, including but not limited to memory PHY interface and HSSI interface with state of the art and cutting edge technology. You will work closely with the product planning & architect for architecture and floor planning, SP&R team for physical implementation, and verification team to review the test plan. You will need to work on post Silicon debug/characterization support of the designs.
• BS/MS or PhD in Electronics Engineering with minimum of 10 years of ASIC front end RTL design
• Minimum 5 years of management experience
• Knowledge on the IP integration & memory interface and HSSI interface design experience is an advantage
• Strong in communication, leadership, investigation, problem solving & analytical skill
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.