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Job ID: JR0008258
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations:
Job Type: Experienced Hire

SoC Design Engineer

Job Description

Come and join us! Intel is seeking highly qualified candidates to join our Data Center Group (DCG) team as a SoC Design Engineer!  You are joining an innovative team in San Jose in which responsible for developing an advance ASSP that helps to drive our Data Center Group road map.  Our organization works on all levels of ASIC development, spanning high-level architecture to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team to contribute to our success.

As a SoC Design Engineer you will oversee definition, design, verification, and documentation for SoC System on a Chip development. As such, you will determine architecture design, logic design, and system simulation as well as define module interfaces/formats for simulation. You will perform Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.  Other responsibilities include contributing to the development of multidimensional designs involving the layout of complex integrated circuits and performing all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.  You will also analyze equipment to establish operation infrastructure, conducts experimental tests, and evaluates results.  You may also review vendor capability to support development.

Additional responsibilities and skills/experience needed for this role include:

1. Be able to develop the actual RTL in System Verilog base on the uArch specification

2. The RTL should be able to synthesize efficiently that meets our timing, area, and power constraint from uArch Specification

3. Review Timing Report from Structural design team, and work with uArch and SD team for timing closure.

4. Work with DV team for DV failure triage, and provide RTL fix.

In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.

The Data Center Group (DCG) drives new products technologies from high-end co-processors for supercomputers to low-energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The group is a worldwide organization that develops the products and technologies that power nine of every 10 servers sold worldwide. 

www.intel.com/jobs/datacenter


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Required Qualifications:
Bachelor Degree in Computer Science, Electrical Engineering, or related discipline with 3+ years of work experience, Masters in Computer Science, Electrical Engineering, or related discipline with 2+ years of work experience.
- 3+ years of experience in high performance ASSP logical design
- 3+ years of proficiency in Verilog or System Verilog.
- 3+ years of experience and understanding of scripting language (Perf, Phython, make file, etc).
- 2+ years of experience developing synthesis script for Synopsys / Cadence too set
- 2+ years of experience developing static timing analysis script.

Additional Preferred Qualifications:
- Experience in Clock Gating, Power Island, and Reset operation is a plus.
- Experience in Java, C, C++ and logical design a plus.
- Excellent written and verbal communication skills.

Inside this Business Group

TBD


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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