As an ASIC Design Engineer (Graduate Trainee), you will be responsible to define & implement the design & validation from front end (linting, CDC, UPF/power gating) to mid end (synthesis, floor planning) of custom digital RTL design and high speed digital design (PCS, SERDES/DPA, DDR, async digital design) in cutting edge technology node. You will work closely with the back-end team for floor planning, physical implementation, STA timing closure and timing model generation using Prime Time. You will need to work on post Silicon debug/characterization support of the designs.
Inside this Business Group
• BS/MS or PhD in Electronics Engineering
• Strong in communication, leadership, investigation, problem solving & analytical skill
• Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments
• Knowledge of scripting is an advantage
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.