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Job ID: JR0005383
Job Category: Engineering
Primary Location: Folsom, CA US
Other Locations:
Job Type: Experienced Hire

Emulation Engineer

Job Description

Creates emulation/Field Programmable Gate Array FPGA models from a Register Transfer Level RTL design using emulation/FPGA synthesis, partitioning and routing tools. Defines and documents RTL changes required for emulation/FPGA. Develops hardware and software collaterals and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals. Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for preSilicon and postSilicon functional validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to presilicon Validation teams for optimizing preSi validation environments, test suites and methodologies for emulation efficiency. Develops and applies automation aids, flows and scripts in support of emulation easeofuse and improvement of equipment utilization.


Qualifications

Minimum Requirements: MS in Electrical Engineering or Computer Science 3+ years of industry experience in emulation and/or logic design and/or verification. Candidate must have 3+ years of experience with the following: -Logic design skills and thorough understanding at gate level -Strong experience in debugging at the system level -Strong understanding of Register Transfer Level RTL design, both at the logic level RTL and gate-level post synthesis -Knowledge of UNIX*, VHDL and Verilog* -Knowledge of synthesis and simulation-Knowledge of scripting and high-level languages like Perl, Python, C/C++ Preferred: - Prior experience in Field Programmable Gate-Array FPGA or Emulation modeling techniques - Designing and validating Bus Functional Models BFMs - Coding and Recoding Register Transfer Level RTL - Building RTL model synthesis, compile, apply design constraints - Debugging tough logic failures at system level - Debugging interfaces like DDR3*, PCI-Express*, and other external/internal buses like SPI, I2C, OCP, UART- Working with internal customers design and system validation teams to define emulation requirements and also provide needed emulation support to customers - Participating in test plan reviews and providing feedback - Participating in the tool development as well as design analysis and debugging using vendor tools - Defining and developing new capabilities to improve emulation

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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