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Job ID: JR0003170
Job Category: Engineering
Primary Location: Eau Claire, WI US
Other Locations: Oregon, Hillsboro;
Job Type: Experienced Hire

Senior Logic Design Engineer

Job Description

Design network physical coding sub-layer and physical layer digital design. Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

Qualifications

BSEE with at least 4+ years of  experience.

Experience Verilog RTL design

Design of high-speed IO PCS and PHY, and experience with network protocols preferred


Qualifications

Inside this Business Group



Other Locations

Oregon, Hillsboro;


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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