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Job ID: JR0003389
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Pre-Silicon Verification Engineer

Job Description
Responsibilities: * Create verification test plans* Develop the architecture and design of the verification environment in OVM/UVM* Develop/run/debug tests and functional coverage in SystemVerilog* Mentor other engineers in using the verification infrastructure and creating test benches* Develop and maintain long term design verification strategy


Qualifications

Professional Knowledge: * 4+ years of hands-on verification experience using SystemVerilog and OVM/UVM* Strong understanding of engineering design principles* Proven track record in ASIC verification from environment development to tests development* Excellent written and verbal communication skillsJob Requirements:* BS in EE or Computer Science, Master's preferred* Experience with creation of plans, schedules and cost estimates for design verification efforts* Experience in development and deployment of verification strategies and methodologies across teams and organizations* Experience with implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage* Proficiency in SystemVerilog* Experience with OVM/UVM must* Proficiency in scripting languages and utilities including Make, Perl, Python, etc.* Expert level knowledge of simulation tools such as VCS from Synopsys* Experience in network ASIC design verification is a plus, such as Ethernet, PCI-Express, InfiniBand, SONET* Experience in C/C++ is highly desirable

Inside this Business Group

TBD

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