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Job ID: JR0001180
Job Category: Engineering
Primary Location: Austin, TX US
Other Locations:
Job Type: Experienced Hire

Senior Memory Design Engineer

Job Description
A Senior Memory Design Engineer is responsible for the design and implementation of Small Signal Array (SSA)/RF compiler for a System-on-chip (SOC) family of products. Responsibilities would include: - Automate RF build and verification flow for the memory compiler - Design and characterize sub arrays for robust operation at extreme corners - Provide design solutions for highest memory density and lowest power solutions


Qualifications

Minimum Qualifications-Must have a BS, MS or PhD in Electrical Engineering or Computer Engineering -4 years' experience with industry standard memory compiler development and all relevant views for the SOC memories -2 years' experience with scripting (Perl, tcl etc.) to develop the compiler and support or enhance the tool as required -4 years' experience in convergence tools including: formal equivalence verification, static timing methodology for SRAM, RF, race check validation, noise and RV -6 years' experience with transistor level operation, SRAM/ sense-amplifier design, design challenges under process variations and low power circuit techniquesPreferred qualifications-4 or more patents and/or publications

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