We have challenging positions as DFx design/validation and ATPG engineers for CDG (Client Development Group) CPU design team. You will be part of the DFx team (Design for testability DFT, manufacturability DFM, debug DFD and validation DFV) and will have an opportunity to influence the way our future CPUs will be tested, validated, and debugged.Responsibilities:In this position you will take part in design and validation of DFx features in one of our future CPUs. Responsibilities will include one or more of the following: Participation in definition of DFx solutions for future test/debug/validation needs.Logic design of DFx units and global debug features within the processor.Logic validation of DFx features at various hierarchy levels.ATPG work for achieving high coverage goals.Supporting Post silicon and yield debug teams
Inside this Business Group
QualificationsYou must possess a Bachelor of Science degree in Electrical Engineering or Computer Engineering. Any experience with VLSI logic design, DFT (SCAN, JTAG, MBIST, etc.) design or validation and ATPG is an advantage. Additional qualifications include: RTL coding or validation experience.C, C++, Object Oriented and Perl programming skills under UNIX.Good communication/interaction skills among groups inside and outside of IsraelEnglish language skills.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.