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Job ID: JR0814684
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

Senior Graphics Hardware Design Engineer

Job Description

If you're interested in computer graphics and working with leading graphics hardware engineers on Intel's latest GPU/CPU architecture, then our Visual and Parallel Computing Group (VPG) has opportunities for you. VPG delivers Intel's 3D graphics, media, display, GPU, and Parallel Computing Technology. This position is in 3D Graphics hardware front-end development where you will be working closely within a team of graphics hardware design/validation engineers, micro-architects, and architects on 3D Graphics blocks (subsystems) targeting a wide range of Intel's future generation processor products. The development environment is dynamic and fast-moving, focused on high-quality results, frequently entailing multiple projects under concurrent development. You will be encouraged to take informed risks, to continuously seek useful design innovations and process improvements, and to have fun while doing so. This position is based in Folsom, CA, whence you will be collaborating with team members and other key partners located across multiple US and international sites. Responsibilities include: -Analysis, interpretation, and assessment of hardware architectural specifications defining feature requirements for 3D Graphics blocks. -Definition and development of microarchitecture specifications, logic designs, and HDL code for 3D Graphics blocks. Design implementations must meet functional and performance requirements, physical/structural design constraints (timing, area, power), as well as proprietary design rules and other quality criteria. -Definition and development of test plans, verification environments, validation components (bus functional models, trackers, checkers, scoreboards, test benches, etc.), functional coverage points, assertions, random and directed tests, random test constraints, etc. to validate 3D Graphics blocks at various levels of integration. -Integration and maintenance of HDL models and verification environments for simulation and ASIC logic synthesis. -Execution and debug of hardware simulations; achievement of functional test coverage objectives. Identification and closure of design and environment defects, including bug fixes requiring manual ECOs (gate-level netlist edits). -Characterization and analysis of performance and power results; implementation of corresponding design modifications and optimizations as required to achieve power and performance targets. -Execution of ASIC logic synthesis flows; implementation of corresponding design modifications and optimizations as needed to achieve timing and area objectives. -Debug of graphics hardware in emulation and/or silicon hardware environments; working with synthetic low-level tests as well as with stimulus from real-world applications and benchmarks and the graphics driver. Behavioral traits for this position include: -Strong communication, interpersonal, and


Qualifications

Candidate should have 10+ years of experience in the following: -Experience in logic design and validation architectures and environment development, ASIC flows. Knowledge of 3D Graphics architecture concepts, APIs, and standards - e.g., Direct3D, OpenGL; media/video codec standards; implementation of vector-based DSP/SIMD algorithms is preferable -Coverage-based validation concepts and application - functional coverage points, assertions, random and directed tests, random test constraints, etc. using System Verilog or similar verification languages/tools; UVM/OVM verification methods -Synopsys ASIC design tools - VCS simulator, Design Compiler, IC Compiler -Formal verification methods - formal property verification (e.g., Jasper), high-level/algorithmic formal equivalence checking (e.g., HECTOR) -High-level hardware modeling using System C, C++; high-level synthesis and optimization (e.g., C-to-Silicon, Catapult, Cynthesizer) -Familiarity with digital hardware emulation and hardware debug tools - emulators, logic analyzers, etc. -Programming or scripting languages such as C/C++, Perl, Ruby, and Python

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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