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Job ID: JR0813614
Job Category: Intern/Student
Primary Location: Hudson, MA US
Other Locations:
Job Type: Intern

Undergrad Intern Physical Design 2017

Job Description
Job Description: Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.Come Intern with the Data Center Group(DCG) and be part of SoC, ASIC development. Responsibilities may include synthesis, automatic place and route, floor planning, timing analysis, integration and design convergence for leading edge Fabric HFI and switch components implemented using Intel's next generation technology.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience.Minimum requirements:- Candidate must be pursuing a BS in Electrical Engineering or Computer Engineering.- Must have unrestricted right to work in the US without requiring sponsorship.- Minimum of 3 months experience with Verilog design languages to target technologies via synthesis, place, and routing tools.- Minimum 3 months experience/knowledge in circuit design and SoC convergence methodology.Preferred Qualifications:- Experience with debugging problems in design flow.- Experience with scripting.

Inside this Business Group

TBD


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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