Job Description: Creates TOP-down, bottom-up elements of VLSI analog layout designs, from floor plan to full custom layout generation. Verify the layout using different flows and tools, including parasitic extraction, static timing analysis , wire load models, clock generation, and polygon editing. Troubleshoot a wide variety of possible issues in the tools, flows and design. The layout work involves interaction with the design group and layout group, working as one team. The team is part of IPG-MIG and in close interaction with other MIG groups around the globe.
Inside this Business Group
Electrical engineer / Electronics engineer.5+ years of experience inAnalog VLSI layout designTeam player with the ability to work under pressure.Good communication skillshigh level of English
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.