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Job ID: JR0809666
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Senior Analog/Mixed-Signal Lead Engineer

Job Description
We are an end-to-end design team based in Bangalore part of the Server Development Group responsible for delivering large and complex processors as well as High-Speed IO IP’s. In this position, you will be responsible for the design, development and validation of mixed signal circuit components on the project. You will be responsible for mixed signal circuit design, circuit checking, device evaluation and characterization, process-aware analog component design, documentation of specifications, prototype construction and checkout, modification and evaluation of semiconductor devices and components, performing developmental and/or test work, reviewing product requirements and logic diagrams, planning and organizing design projects or phases of design projects. The responsibilities will span multiple process generations and designs include QPI, PCI-express, DDR, temperature sensor, etc. In addition, you will be mentoring and supervising junior design engineers.


Qualifications

You must possess a Master of Science (or a Master of Technology) degree with a minimum of Ten years experience in analog and mixed signal circuit design with a focus on high-speed serial I/O interfaces. Publications and patents in relevant fields would be an added advantage. - Work experience and knowledge of Single-ended memory interfaces (DDR3/DDR4, etc), including transmitter, receiver, Clock distribution, ADC and DAC circuit design, feedback systems and the ability to analyze channel effects such as crosstalk as well as power delivery impact on signal integrity - Prior experience with the design of high speed I/O 5Gbps (Receiver, Transmitter, DLL, Clock Recovery, Jitter analysis, and Equalization schemes) would be an added advantage- Expertise in bench evaluation and measurements techniques for Bit-Error-Rate and Jitter.- Experience in integrating complex analog blocks in baseline digital process technologies to meet high-volume manufacturing quality standards- Expertise in transistor-level analog design, block-level integration, and architecture tradeoffs (tools: Cadence* Suite, ADE*) - An in-depth knowledge of analog layout techniques, including matching, offset minimization, parasitic optimization and floor planning, combined with experience of deep submicron technologies. - High voltage tolerant circuit design and Electrostatic Discharge (ESD) protection strategies - Ability to implement Matlab* models of interface link, including: signaling for worst case ISI, channel ISI, jitter budgets, Bit Error Rate (BER), bathtub curves, and others - Proficiency in process/device/technologyProven record of technical leadership.- Good and clear understanding of the industry trends and issues regarding memory interfaces and to help provide direction to the team - Innovative thinking, problem solving, good communication skills, self discipline and results orientation are critical soft-skills needed - Demonstrated ability to work in a demanding team-oriented environment - Mentor junior engineers in all aspects of design

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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