Engineer - Design for Testability

Job Description
Job Description: Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

Qualifications

Master's degree in Electronics/Electrical Engineering, with concentration on Communications, Signal Processing and VLSI Design 2 years of industry experience in design for testability Candidate should possess strong digital design and VLSI fundamentals with prior experience in DFT. Knowledge of VHDL, Verilog, C/System-C/System-Verilog/Specman, micro-architecture development, Signal processing, filters, data-path designs, communication systems standards (DSL, WLAN, Ethernet), processor IP cores (MIPS, ARC), high-speed interfaces (USB, PCIe, DDR, xGMII) and ASIC design flow (RTL to GDS) would be desirable.

Inside this Business Group

The Client Computing Group is responsible for all aspects of the client computing business across Phone, Phablet, Tablet and PC platforms, leading Intel's efforts to transform client computing through technologies, new form factors, and driving Intel's corporate-wide user experience initiatives. This spans all client device brands including hardware, software and connectivity ingredients for phones, tablets, Ultrabook™, All-in-Ones, 2 in 1 computing devices, and home gateways.