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Job ID: JR0809417
Job Category: Engineering
Primary Location: Phoenix, AZ US
Other Locations:
Job Type: Experienced Hire

RTL Design and Verification Engineer

Job Description

Intel Datacenter Power and Package Solutions group is looking for an experienced digital design and verification engineer with experience in the fields of mixed-signal or power electronics. What you'll do Your job will be to architect, model, simulate, test, and bring to production digital-interfaces and sequencing controllers for use in state-of-the-art power-delivery solutions. You will need to communicate with external suppliers in power-delivery solution implementation, providing design guidance and helping to verify their design implementation. Although this job does not entail much travel, you must be willing and able to travel globally to vendor and customer sites. The successful candidate will be a key contributor to the design and pre-silicon functional verification of state-of-the-art power management ICs. Your responsibilities will include but not be limited to: -Design and Pre-Si verification, including leading Verilog digital behavioral modeling of mixed-signal and analog systems. In this case, specifically PMIC and VRs. -RTL design and leading implementation of controller for mixed-signal chips -Developing synthesizable, accelerated, analog behavioral-models for representing PMIC behavior in Pre-Si SoC/ASIC environments -Ownership of Pre-Si functional verification of subsystems and/or complete chips -Debugging if behaviors are caused by errors in the specs, models, design implementation, or tests -Writing verification plans -Writing and maintaining behavioral models and test benches in Verilog -Writing technical documentation and presentation -Debugging systems utilizing encrypted RTL from external sources -Requirements management


Qualifications

Masters / Bachelor's Degree in Electrical Engineering or related degree, with 5+ years of relevant industry experience. -5+ years of experience in mixed-signal IC logic design and verification -5+ years of experience writing and fluency in either Verilog or VHDL languages, Verilog and System Verilog heavily preferred over VHDL. -3+ years of experience developing behavioral models of analog circuitry -5+ years of experience drafting technical specifications, good English writing and speaking skills -1+ years of leading digital design within a mixed-signal IC design project. Additional Qualifications: -Leadership skills -Excellent experience and understanding of power management IC (PMIC). -Experience writing RTL for power management ICs. -Experience with analog / digital co-simulation tools such as AMS Ultrasim. -Experience utilizing emulation platforms such as Mentor Graphics Veloce. -Experience writing synthesizable RTL simulation models for analog components -including VRs, DACs, and ADCs within a larger digital environment. -Ability to create and evaluate synthesis/build and simulation tool flows -Experience putting together a simulation / regression environment. -Experience debugging externally sourced IP from encrypted models.

Inside this Business Group

TBD


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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